We Design Customizable and Reconfigurable SoCs

Your Vision, Our Innovation.

Platform

The agile platform for RISC-V SoCs, streamlining innovation with seamless reconfigurability and efficiency. Empower your vision with our flexible, next-gen technology solutions.

Customization

Brings the power of precise customization to your fingertips, offering unmatched control over instruction-level customization alongside optimal power, frequency, and area management.

Automation

Elevates design automation, transforming RTL into GDS with precision. Our platform includes comprehensive self-testing capabilities to ensure optimal performance and reliability.

Explore our Tool

Our goal is to enhance the CPU-architects to design the RISC-V SoC without worrying about underlying details. Our tool can generate a full RISC-V compliant SoC and even a minute subset of RISC-V ISA type to support and enhance your performance.

Customizable SoC Design

An innovative platform for designing and optimizing custom RISC-V System-on-Chip (SoC) w.r.t the application and performance requirements in very less time.

Reconfigurable Hardware Acceleration

Our tool also supports convinent insertion of complex computation accelerators and interface with the C code with new set of instructions for your hardware.

Explore RISC-V

Meet Best People

Mayank Kabra

Founder
(ETH Zurich)

Kunal Ghosh

Advisor
(VLSI System Design)

Madhav Rao

Advisor
(Prof @ IIIT Bangalore)

Asmita Zjigyasu

Co-founder
(IIIT Bangalore)

Siddharth Kothari

RISC-V Architect
(IIIT Bangalore)

Sankalp Kothari

RISC-V Architect
(IIIT Bangalore)

Mohammad Abdul

FPGA Engineer
(University of Hyderabad)

Abdul Mannan

Analog Engineer
(RVCE Bangalore)

Our Work in Collaboration with IIIT Bangalore

Iswarya I : GitHub Digital Alarm Clock
Nitesh Sharma : GitHub Anti-theft Compartment
Vartika Barnwal : GitHub Smart HVAC System
Shant Rakshit : GitHub Passcode Based Authenticator for Locker
Alwin Shaju : GitHub Contactless Water Level Controller
Bhargav D V : GitHub Display Controller
Amith Bharadwaj : GitHub Hall Effect Sensor-based Door Alarm System
Kanish R : GitHub Automatic Sanitizer Dispenser

For More Projects: Click Here

Our Joint Workshop

Join us for a transformative 6-week journey exploring the depths of RISC-V ISA and its application in product-based environments. Master end-to-end application design to RTL with RISC-V and using our Chipcron tool in our comprehensive six-week workshop

Registration Fees

$ 149 10th May to 21st Jun 2024

    Join us for a transformative 6-week journey
    exploring the depths of RISC-V ISA and
    its application in product-based environments.

Course Outcome

End-to End-Product from specification to RTL IP design and tapeout.

Pavan Kumar Arekere : GitHub RISC-V: Hardware Design Program
David Brough-Smyth : GitHub RISC-V: Hardware Design Program
Soham Bhattacharya : GitHub RISC-V: Hardware Design Program
Jaya Chelani : GitHub RISC-V: Hardware Design Program

Publications and Patents


Patent 1 - 202341044354: Granted - 20/03/2024 - RISC-V based system and method for assisting visually impaired.

Patent 2 - 202341036595: Filled - 30/06/2023 - A system and methods for cutomizing integrated circuit designs.

Publications - Check here

Contact Us